Chapter 4: CPU and ISA — The Core Engine

Vol 3: Computer Core Expedition · Chapter 4

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Metadata Card

Attribute	Value
Difficulty	(5/5)
Prerequisites	Digital Logic (Chapter 3); C basics
Keywords	Instruction Cycle, RISC-V ISA, Datapath, RISC vs CISC

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Your Progress

"One layer above the logic gates, you've reached the engine room of the Core — the CPU. It endlessly reads instructions from memory, decodes them, and executes them. Every line of Java code you wrote in Variable Village ends up being translated into machine instructions by this engine."

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Encounter 1: From C to Assembly

int add(int a, int b) {
    return a + b;
}

Compiled to RISC-V:

add:
    addi sp, sp, -8
    sw   s0, 4(sp)
    addi s0, sp, 8
    sw   a0, -8(s0)
    sw   a1, -4(s0)
    lw   a5, -8(s0)
    lw   a4, -4(s0)
    add  a5, a5, a4
    mv   a0, a5
    lw   s0, 4(sp)
    addi sp, sp, 8
    ret

With -O2: just add a0, a0, a1 + ret.

Encounter 2: Instruction Cycle (5 Stages)

1. IF (Instruction Fetch): PC → instruction memory → 32-bit instruction
2. ID (Instruction Decode): Decode instruction → read registers → generate immediates
3. EX (Execute): ALU operation / address calculation
4. MEM (Memory Access): Read/write data memory (load/store only)
5. WB (Write Back): Write result to register file

Encounter 3: RISC vs CISC

Dimension	RISC-V	x86
Instruction length	Fixed 32-bit	Variable 1-15 bytes
Registers	32 general-purpose	16 (x64)
Memory operations	Load/store only	ALU can operate on memory
Decoder complexity	Low (uniform format)	Very high (prefix, microcode)
Typical chip area	Decoder < 5%	Decoder ≈ 20-30%

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Verification Checklist

• [ ] Can explain the 5-stage instruction cycle
• [ ] Can read basic RISC-V assembly
• [ ] Can explain RISC vs CISC core philosophy differences (at least 3)

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Traveler's Notes

• The CPU executes binary representations of instructions, not "code"
• ISA is a contract: hardware promises to execute semantics, software promises valid instructions
• Modern x86 CPUs are RISC cores internally — CISC instructions get decoded into micro-ops

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Chapter 5: Cache and Memory Hierarchy — Speed Buffers