Chapter 15: CPU Pipeline

Vol 3: Computer Core Expedition · Chapter 15

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Metadata Card

Attribute	Value
Keywords	5-Stage Pipeline, Hazards, Forwarding, Branch Prediction, Out-of-Order Execution

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Your Progress

"The single-cycle CPU is slow because every instruction takes the same long clock period. The pipeline breaks each instruction into stages, allowing multiple instructions to overlap — one finishes every cycle."

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Encounter 1: 5-Stage Pipeline

Instruction 1: IF  ID  EX  MEM  WB
Instruction 2:     IF  ID  EX   MEM  WB
Instruction 3:         IF  ID   EX   MEM  WB

Throughput: 1 instruction per cycle (ideally).

Encounter 2: Hazards

1. Structural hazard: Two instructions need the same hardware resource
2. Data hazard: An instruction depends on a previous instruction's result
   • RAW (Read After Write): Most common, solved by forwarding
   • WAR / WAW: Write ordering issues
3. Control hazard: Branch instructions change the program flow

Encounter 3: Forwarding (Bypassing)

Instead of waiting for a result to be written to the register file, forward it directly from the EX stage to the next instruction's EX stage. Eliminates most data hazards.

Encounter 4: Branch Prediction

Predict whether a branch will be taken before the condition is resolved:

• Static: Always predict not taken / taken
• Dynamic: Use history (2-bit saturating counter, tournament predictors)

Misprediction penalty: Pipeline flush (wasted cycles).

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Verification Checklist

• [ ] Can draw the 5-stage pipeline
• [ ] Can identify different hazard types
• [ ] Can explain forwarding
• [ ] Can describe branch prediction and its importance

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Chapter 16: C and the Memory Model